above feelings

作者: koykoy (Nobody Knows) 看板: P_koykoy
標題: Re: verilog
時間: Fri May 26 01:23:55 2006

//NCTU-EE VLSI2006 Group-32 Lab3

//Top Module for 16-bit accmulator
module MAC8(A,B,ACC,OUT);
input [7:0] A,B;
input [15:0]ACC;
output [16:0]OUT;
wire [8:0]pa0,pa1,pa2,pa3;
wire [15:0]pp0,pp1,pp2,pp3,pp4;
wire [15:0]sa,sb,sc,sd;
wire [15:0]ca,cb,cc,cd;

PPa p0({A[1:0],1'b0},B[7:0],pa0[8:0]);
PPa p1(A[3:1],B[7:0],pa1[8:0]);
PPa p2(A[5:3],B[7:0],pa2[8:0]);
PPa p3(A[7:5],B[7:0],pa3[8:0]);

//sign-extend
assign pp0[15:0]={{7{pa0[8]}},pa0[8:0]};
assign pp1[15:0]={{5{pa1[8]}},pa1[8:0],1'b0,pa0[8]};
assign pp2[15:0]={{3{pa2[8]}},pa2[8:0],1'b0,pa1[8],2'b0};
assign pp3[15:0]={pa1[8],pa1[8:0],1'b0,pa2[8],4'b0};
assign pp4[15:0]={9'b0,pa3[8],6'b0};

CSA_16b csaa(pp0[15:0],pp1[15:0],pp2[15:0],sa[15:0],ca[15:0]);
CSA_16b csab(pp3[15:0],pp4[15:0],ACC[15:0],sb[15:0],cb[15:0]);
CSA_16b csac(sa[15:0],{ca[14:0],1'b0},sb[15:0],sc[15:0],cc[15:0]);
CSA_16b csad(sc[15:0],{cc[14:0],1'b0},{cb[14:0],1'b0},sd[15:0],cd[15:0]);
FA_16b faa(sd[15:0],cd[15:0],OUT[16:0]);

endmodule




//1bit full-adder
module FA(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire t1,t2,t3;

xor #(0.7,0.7) (sum,a,b,cin)
nand #(0.4,0.4) (t1,a,b);
nand #(0.4,0.4) (t2,b,cin);
nand #(0.4,0.4) (t3,a,cin);
nand #(0.5,0.5) (cout,t1,t2,t3);
endmodule



//16-bit ripple carry adder with CLA4
module FA_16b(a,b,c);
input [15:0]a,b;
output [16:0]c;
wire [2:0]carry;

CLA4 c1(c[3:0],carry[0],a[3:0],b[3:0],1'b0);
CLA4 c2(c[7:4],carry[1],a[7:4],b[7:4],carry[0]);
CLA4 c3(c[11:8],carry[2],a[11:8],b[11:8],carry[1]);
CLA4 c4(c[15:12],c[16],a[15:12],b[15:12],carry[2]);

endmodule



//carry look ahead adder
module CLA4(s,cout,a,b,cin);
output [3:0]s;
output cout;
input [3:0]a,b;
input cin;
wire [3:0]g,p,x;
wire [3:1]h;


and #(0.5,0.5) (g[3],a[3],b[3]);
and #(0.5,0.5) (g[2],a[2],b[2]);
and #(0.5,0.5) (g[1],a[1],b[1]);
and #(0.5,0.5) (g[0],a[0],b[0]);

or #(0.5,0.5) (p[3],a[3],b[3]);
or #(0.5,0.5) (p[2],a[2],b[2]);
or #(0.5,0.5) (p[1],a[1],b[1]);
or #(0.5,0.5) (p[0],a[0],b[0]);

and #(0.5,0.5) (x[0],p[0],cin);
or #(0.5,0.5) (h[1],x[0],g[0]);
and #(0.5,0.5) (x[1],p[1],h[1]);
or #(0.5,0.5) (h[2],x[1],g[1]);
and #(0.5,0.5) (x[2],p[2],h[2]);
or #(0.5,0.5) (h[3],x[2],g[2]);
and #(0.5,0.5) (x[3],p[3],h[3]);
or #(0.5,0.5) (cout,x[3],g[3]);

xor #(0.7,0.7) (s[0],a[0],b[0],cin);
xor #(0.7,0.7) (s[1],a[1],b[1],h[1]);
xor #(0.7,0.7) (s[2],a[2],b[2],h[2]);
xor #(0.7,0.7) (s[3],a[3],b[3],h[3]);

endmodule



//16-bit carry save adder
module CSA_16b(p,q,r,s,c)
input [15:0]p,q,r;
output [15:0]s,c;

FA fa15 (p[15],q[15],r[15],s[15],c[15]);
FA fa14 (p[14],q[14],r[14],s[14],c[14]);
FA fa13 (p[13],q[13],r[13],s[13],c[13]);
FA fa12 (p[12],q[12],r[12],s[12],c[12]);
FA fa11 (p[11],q[11],r[11],s[11],c[11]);
FA fa10 (p[10],q[10],r[10],s[10],c[10]);
FA fa9 (p[9],q[9],r[9],s[9],c[9]);
FA fa8 (p[8],q[8],r[8],s[8],c[8]);
FA fa7 (p[7],q[7],r[7],s[7],c[7]);
FA fa6 (p[6],q[6],r[6],s[6],c[6]);
FA fa5 (p[5],q[5],r[5],s[5],c[5]);
FA fa4 (p[4],q[4],r[4],s[4],c[4]);
FA fa3 (p[3],q[3],r[3],s[3],c[3]);
FA fa2 (p[2],q[2],r[2],s[2],c[2]);
FA fa1 (p[1],q[1],r[1],s[1],c[1]);
FA fa0 (p[0],q[0],r[0],s[0],c[0]);
endmodule




//pp before sign extended
module PPa(a,b,c);
input [2:0]a;
input [7:0]b;
output [8:0]c;

BO booth0(a[2:0],{b[0],1'b0},c[0]);
BO booth1(a[2:0],b[1:0],c[1]);
BO booth2(a[2:0],b[2:1],c[2]);
BO booth3(a[2:0],b[3:2],c[3]);
BO booth4(a[2:0],b[4:3],c[4]);
BO booth5(a[2:0],b[5:4],c[5]);
BO booth6(a[2:0],b[6:5],c[6]);
BO booth7(a[2:0],b[7:6],c[7]);
BO booth8(a[2:0],{1'b0,b[7]},c[8]);
endmodule





//radix-4 booth algorithm for each bit
module BO(a,b,c);
input [2:0]a;
input [1:0]b;
output c;
wire p,q,r,s,t,u,v,w,x,y,z;

xor #(0.6,0.6) (p,a[0],a[1])
not #(0.2,0.2) (q,a[2]);
not #(0.2,0.2) (r,a[1]);
not #(0.2,0.2) (s,a[0]);
nand #(0.5,0.5) (t,q,a[1],a[0]);
nand #(0.5,0.5) (u,a[2],r,s)
nand #(0.4,0.4) (v,t,u);
and #(0.5,0.5) (w,b[1],p)
and #(0.5,0.5) (x,b[0],v)
nor #(0.4,0.4) (y,w,x);
xor #(0.6,0.6) (z,y,a[2])
not #(0.2,0.2) (c,z);
endmodule
--
夫兵者不祥之器物或惡之故有道者不處君子居則貴左用兵則貴右兵者不祥之器非君子
之器不得已而用之恬淡為上勝而不美而美之者是樂殺人夫樂殺人者則不可得志於天下
矣吉事尚左凶事尚右偏將軍居左上將軍居右言以喪禮處之殺人之眾以哀悲泣之戰勝以
喪禮處之道常無名樸雖小天下莫能臣侯王若能守之萬物將自賓天地相合以降甘露民莫
之令而自均始制有名名亦既有夫亦將知止知止可以不殆Tears.Dorm13.NCTU.edu.tw海